An AI accelerator card concentrates more electrical and thermal stress into a single PCB than almost any other product in electronics. A single high-end accelerator can draw several hundred amps, dissipate hundreds of watts, route thousands of high-speed signals, and connect a package with thousands of balls — all on one board that must stay flat, cool, and electrically clean. Three challenges dominate the design: getting power in, getting heat out, and fitting the routing in. This article looks at each.
It is the third article in our AI hardware series, joining our pieces on the high-layer-count boom and the broader supply pressure AI is creating. This one focuses on the board-level design challenges themselves. Linked Electronics Co., Limited manufactures the high-layer-count, heavy-copper, high-speed boards that accelerator cards demand, and reviews each design against the constraints below.
Challenge One: Power Delivery
The defining electrical challenge of an AI accelerator is power. A processor drawing 400–700 watts at under one volt is pulling several hundred amps through the board. Delivering that current cleanly, without excessive voltage drop or noise, is the single hardest part of the design.
The IR Drop Problem
Voltage drop across copper (IR drop) scales with current. At hundreds of amps, even milliohms of plane resistance produce meaningful voltage loss before power reaches the processor core — and the core's operating voltage window is narrow. The design must deliver power with minimal resistance, which means wide, thick copper planes and many parallel paths. Insufficient copper means the processor browns out under load.
Heavy Copper Planes
To carry hundreds of amps, AI boards use heavy copper power and ground planes — 2 oz, 3 oz, or heavier copper rather than the standard 1 oz. Multiple such planes distributed through the stackup share the current and reduce resistance. This heavy copper is one reason AI accelerator boards are both thick and high-layer-count. Linked Electronics Co., Limited produces heavy copper multilayer boards as a core capability.
The Power Delivery Network (PDN)
Beyond raw DC delivery, the processor's current demand changes rapidly as compute load shifts — nanosecond-scale transients. The power delivery network must supply these transients without the voltage sagging, which requires a carefully designed hierarchy of decoupling capacitors from bulk electrolytics down to small MLCCs placed as close to the processor power pins as possible. This is why AI boards carry thousands of MLCCs and why via-in-pad is used on the decoupling caps to minimise inductance — a topic covered in our via-in-pad article.
Plane Capacitance and Via Density
Power and ground planes spaced closely together form a distributed capacitor that supplies the fastest transients. Connecting the processor to these planes requires a dense field of power and ground vias under the package. The via design here directly affects PDN performance, and on a high-layer-count board it interacts with the overall via strategy.
Challenge Two: Thermal Management
The power that goes in comes out as heat. An accelerator dissipating 500 watts must move that heat off the silicon, through or around the board, and into a heatsink or liquid-cooling system — without the board itself becoming a thermal bottleneck or warping under the gradient.
Thermal Vias
Heat from the processor and from power components must be conducted away. Thermal vias — dense arrays of copper-filled vias under hot components — carry heat through the board to internal planes or to the opposite side. Copper-filled (IPC-4761 Type VII) vias conduct heat far better than hollow plated vias, which is why they are standard under high-power components. Our via types article covers the fill options.
Heavy Copper as a Heat Spreader
The same heavy copper planes that deliver power also spread heat. Thick internal copper acts as a lateral heat spreader, moving heat away from hot spots toward cooler regions and toward thermal interfaces. This dual role — power delivery and heat spreading — is part of why heavy copper is central to accelerator board design.
Warpage Under Thermal Gradient
A board with a 500-watt hot spot in the centre and cooler edges experiences thermal expansion gradients that drive warpage. Warpage stresses solder joints — especially the large BGA under the processor — and can crack joints over thermal cycles. Managing this requires balanced stackup design, appropriate material selection (high-Tg, low-CTE laminates), and sometimes stiffeners. Linked Electronics Co., Limited reviews stackup symmetry and material choice for warpage control on high-power boards.
Material Thermal Limits
The laminate must survive both the assembly reflow and the operating temperature over years. High-Tg and high-Td materials resist the thermal stress better than standard FR4. For accelerator boards combining high power with high-speed signals, the material must satisfy both thermal and electrical requirements simultaneously — often a high-speed laminate with good thermal properties, as discussed in our material selection guide.
Challenge Three: Layer Count and Routing
The third challenge is simply fitting everything in. Power planes, ground planes, thousands of high-speed signals with their reference planes, and the escape routing from a massive BGA all compete for layers.
The Layer Budget
An accelerator board's layer count is the sum of its routing demands: signal layers for high-speed buses (each needing adjacent reference planes), multiple heavy copper power and ground planes, and BGA escape layers. These add up quickly to 20, 30, or more layers. The high-layer-count fabrication challenges — registration, lamination, aspect ratio, yield — are covered in detail in our high-layer-count article.
High-Speed Signal Integrity
The data buses on an accelerator — HBM interfaces, chip-to-chip links, host PCIe — run at 25G, 56G, or 112G. These require low-loss or ultra-low-loss laminate, controlled impedance, back-drilling of via stubs, and careful reference plane management. Signal integrity on these layers cannot be compromised to save layers or cost. Our articles on Dk/Df, back-drilling, and signal degradation cover these requirements.
The Interlocking Constraint
What makes accelerator board design genuinely hard is that the three challenges interact. Heavy copper for power makes the board thicker, which worsens via aspect ratio for signal routing. High layer count for routing increases lamination complexity and warpage risk. Thermal vias compete for space with signal routing under the BGA. No single challenge can be solved in isolation — the design is a simultaneous optimisation across power, thermal, and routing, and the fabricator must understand all three.
Summary of Design Challenges
| Challenge | Driver | PCB Response |
|---|---|---|
| Power delivery | Hundreds of amps at low voltage | Heavy copper planes, dense PDN, via-in-pad decoupling |
| Thermal | Hundreds of watts dissipated | Thermal vias, heavy copper spreaders, high-Tg material |
| Layer count | Thousands of pins and high-speed pairs | 20–40 layers, mixed via technology |
| Signal integrity | 25G–112G data rates | Low-loss laminate, back-drilling, impedance control |
Frequently Asked Questions
Why do AI accelerator cards need heavy copper?
Because they draw hundreds of amps. Standard 1 oz copper cannot carry that current without excessive resistance and voltage drop. Heavy copper planes (2 oz and above) reduce resistance, share current across parallel paths, and double as heat spreaders. Linked Electronics Co., Limited produces heavy copper multilayer boards for exactly this kind of high-current application.
What is a power delivery network (PDN)?
The PDN is the complete path that delivers clean, stable power from the board's input to the processor core — including planes, vias, and the hierarchy of decoupling capacitors that supply fast current transients. A well-designed PDN keeps the core voltage stable as compute load changes rapidly. On AI boards, the PDN is one of the most demanding parts of the design.
How is heat removed from an AI accelerator board?
Through a combination of thermal vias (copper-filled vias conducting heat through the board), heavy copper planes acting as lateral heat spreaders, and external heatsinks or liquid cooling attached to the components. The PCB's job is to conduct heat efficiently from the hot silicon to the thermal interface without becoming a bottleneck.
Why are these boards so many layers?
The layer count sums the demands of high-speed signal routing (each signal layer needs reference planes), heavy copper power and ground planes, and escape routing from a massive BGA. Together these push accelerator boards to 20–40 layers. See our dedicated high-layer-count article for the fabrication implications.
Can one fabricator handle power, thermal, and high-speed requirements together?
This is exactly the point — accelerator boards require a fabricator competent in heavy copper, high layer count, and high-speed materials simultaneously, because the requirements interact. A shop strong in only one area will struggle. Linked Electronics Co., Limited combines heavy copper, high-layer-count, and high-speed laminate capability and reviews accelerator designs against all three constraints together.
Does Linked Electronics Co., Limited build AI accelerator boards?
Linked Electronics Co., Limited manufactures the high-layer-count, heavy-copper, high-speed multilayer boards that AI accelerator and GPU cards require, with thermal via, via-in-pad, back-drilling, and controlled-impedance capability. We provide DFM review covering power delivery copper, thermal via strategy, layer count, and high-speed material selection. Contact us to discuss capability for your accelerator design.
Why Choose Linked Electronics Co., Limited for AI Accelerator Boards
Linked Electronics Co., Limited brings together the three capabilities AI accelerator boards demand in one facility: heavy copper fabrication for high-current power delivery, high-layer-count multilayer construction with mixed via technology, and qualified high-speed laminate processing for signal integrity. Because accelerator design is a simultaneous optimisation across power, thermal, and routing, our engineering team reviews all three together at quotation rather than treating them as separate problems.
Every accelerator-class board benefits from our thermal via and via-in-pad capability for power and heat, our heavy copper plane fabrication for current delivery, our back-drilling and impedance control for high-speed signals, and our high-layer-count registration and lamination control. All boards receive 100% electrical test, microsection coupon verification, and X-ray inspection of internal structures and BGA joints.
If you are developing an AI accelerator card, GPU board, or any high-power high-speed design, send your stackup, Gerber files, power requirements, and target data rates to [email protected]. Linked Electronics Co., Limited will return a manufacturability assessment addressing power, thermal, and routing together, with a quote for prototype and production volumes.
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