How PCB Laminate Df (Loss Tangent) Kills Your Signal at 10 GHz and Above

A 25 Gbps SerDes channel passes simulation. The transmitter has 50% pre-emphasis, the receiver has CTLE enabled, the trace is impedance-matched to 100 ohms differential, and the via stubs were back-drilled. The board arrives, the team powers it up, the link trains successfully at 12 Gbps and refuses to go higher. Hours of bring-up reveal eye height collapsing well below the receiver tolerance threshold. The schematic is clean. The layout is clean. Where did the signal go?

The signal got absorbed by the dielectric. Every inch of FR4 between transmitter and receiver took a slice of the high-frequency content of the data stream and converted it into a small amount of heat. By the time the signal arrived at the receiver, the eye was closed at the frequencies that carried the bits.

This article explains how dielectric loss — quantified by the laminate's Df, or loss tangent — actually kills high-speed signals once frequencies cross roughly 10 GHz, why this threshold matters, and what design choices recover the lost margin. It is the companion article to our Dk and Df fundamentals guide; this one focuses on the failure mode, not the parameter.

The Mechanism: Dielectric Absorption

When a high-frequency signal travels along a PCB trace, the electromagnetic field extends into the surrounding dielectric. Inside the dielectric, the field interacts with the polar molecules of the resin and reinforcement — tugging them, rotating them, polarising them. Each interaction extracts a small amount of energy from the wave and converts it to molecular kinetic energy — heat.

The fraction of energy lost per cycle of the wave is what Df captures. A Df of 0.020 means roughly 2% of the wave energy is lost per radian of phase advance through the material. The same wave passing through Df = 0.002 material loses only 0.2% per radian.

This sounds small. It is not, once you account for the multiplier: total channel loss compounds the per-radian loss across every radian of phase that the wave accumulates. A wave at 10 GHz traveling 10 inches through FR4 accumulates approximately 5500 radians of phase. Two percent loss per radian leaves vanishingly little signal at the far end.

The practical relationship for dielectric loss in dB per inch of trace is:

Loss (dB/inch) ≈ 2.3 × f(GHz) × sqrt(Dk) × Df

Three observations from this equation drive everything else in this article:

• Loss scales linearly with frequency. Double the frequency, double the loss per inch — before considering anything else.
• Loss scales linearly with Df. A material with twice the Df has twice the loss at the same frequency.
• Loss scales with trace length. Total channel loss is loss-per-inch multiplied by trace length.

The compounding effect is what makes 10 GHz a critical inflection point.

Why 10 GHz Is the Threshold

The frequency content of a digital data stream is dominated by its Nyquist frequency — half the data rate for NRZ signalling. PCIe Gen3 at 8 Gbps has a Nyquist frequency of 4 GHz; the channel needs to faithfully transmit content up to and somewhat beyond this. PCIe Gen4 at 16 Gbps has Nyquist 8 GHz. 25G NRZ SerDes has Nyquist 12.5 GHz. 56G PAM-4, despite the higher data rate, has fundamental rate 28 Gbaud and Nyquist around 14 GHz. PCIe Gen5 at 32 Gbps NRZ has Nyquist 16 GHz. PCIe Gen6 at 64 Gbps PAM-4 has Nyquist around 32 Gbaud and Nyquist content well above 16 GHz.

Now apply the loss equation. A 10 inch FR4 channel (Dk 4.3, Df 0.020):

• At 4 GHz: 3.8 dB loss — manageable
• At 8 GHz: 7.6 dB loss — getting tight
• At 12.5 GHz: 11.9 dB loss — channel margin gone
• At 16 GHz: 15.2 dB loss — non-functional without aggressive equalisation

Compare a 10 inch Megtron 6 channel (Dk 3.6, Df 0.0040) at the same frequencies:

• At 4 GHz: 0.7 dB loss
• At 8 GHz: 1.4 dB loss
• At 12.5 GHz: 2.2 dB loss
• At 16 GHz: 2.8 dB loss

This is not a small refinement. It is a factor of five reduction in dielectric loss at every frequency. The same channel topology, same geometry, same equalisation — only the material was changed. The board that fails on FR4 succeeds on Megtron 6.

Below 10 GHz, FR4 is usually adequate. Above 10 GHz, FR4 becomes the bottleneck. The 10 GHz threshold is not a sharp wall but it is where loss-per-inch with high-Df materials crosses the level where receiver equalisation alone can no longer recover the signal.

What Signal Degradation Actually Looks Like

Insertion Loss

Insertion loss is the headline measurement — the dB attenuation between transmitter and receiver, measured by S21 in a vector network analyser. Channel specifications from IC vendors typically state a maximum allowable insertion loss at the Nyquist frequency. PCIe Gen5 limits channel insertion loss to approximately 36 dB at 16 GHz, including all PCB traces, vias, connectors, and package routing. The PCB has a budget; if the laminate eats the whole budget, the connector and package have none.

Eye Diagram Closure

The receiver sees the signal as a time-domain eye opening — the rising edges and falling edges of consecutive bits forming an "eye" with a clear opening in the middle. Dielectric loss attenuates the high-frequency content of these edges, slowing them. The eye opening shrinks both vertically (amplitude collapse) and horizontally (timing jitter from slower edges). When the eye closes below the receiver's specified tolerance, the receiver cannot reliably distinguish a 1 from a 0 at the centre of the bit period.

Bit Error Rate (BER)

The end consequence is bit error rate. As the eye closes, the probability that random noise pushes a sample over the decision threshold rises. A channel with comfortable eye margin runs at BER 10^-15 or better — effectively error-free. A channel running 3 dB over its loss budget might run at BER 10^-9 — one error in every billion bits, which for a 25 Gbps link means an error every 40 milliseconds. Operating systems and network layers can usually mask this, but for low-latency hardware it manifests as link retries, framing errors, or hard link drops.

Equalisation Burden

Modern SerDes receivers include CTLE (continuous-time linear equalisation), DFE (decision feedback equalisation), and sometimes FFE (feedforward equalisation) in the transmitter. These boost high-frequency content to compensate for dielectric loss. They are powerful but they have limits — each has a maximum boost ratio beyond which residual noise becomes dominant. As channel loss climbs, equalisation has to work harder, and at some point the noise penalty from boosting equals the loss it is compensating. That is the practical ceiling.

The Frequency Multiplier Effect in Practice

The compounding nature of loss makes channel design unforgiving above 10 GHz. A concrete example: a 12 inch backplane channel carrying 25 Gbps NRZ.

On standard FR4 (Df 0.020): dielectric loss alone is about 14 dB at 12.5 GHz. Add conductor loss from skin effect (roughly 6 dB on standard ED copper at this frequency and length), and via discontinuities (1–2 dB if back-drilled, 4–6 dB if not). Total channel loss can easily exceed 22 dB. The IC vendor specifies maximum 25 dB. Margin is 3 dB — one bad solder joint or one un-back-drilled via and the channel fails.

On Megtron 6 (Df 0.0040): dielectric loss is 2.8 dB. Conductor loss on VLP copper is 4 dB. Vias back-drilled adds 1 dB. Total: 7.8 dB. Against the same 25 dB budget, this leaves 17 dB of margin for connectors, package, and any process variation. The same channel suddenly becomes engineering-comfortable rather than knife-edge.

The margin is not a luxury. Process variation in production — etching tolerances, dielectric thickness variation, copper foil lot-to-lot variation, moisture absorption — can move channel loss by 2–4 dB across a production run. A design that simulated at 22 dB might ship at 24 dB or 26 dB on any given board. The board at 26 dB fails. Material choice that gives 7.8 dB nominal loss leaves room for these variations; material choice that gives 22 dB nominal loss does not.

What Else Adds to Channel Loss

Df is the dominant factor at high frequency but not the only one. The full channel loss breakdown:

Conductor Loss (Skin Effect)

At GHz frequencies, current flows in the outer layer of the conductor — the skin depth in copper at 10 GHz is approximately 0.65 microns. If the copper surface in contact with the dielectric is rough (as it is for standard electrodeposited foil with a 6–9 micron tooth profile for adhesion), the current path is forced to follow that roughness, adding length and resistance. The contribution can be 30–100% of the smooth-copper conductor loss at high frequency. For low-loss designs, very-low-profile (VLP), reverse-treated (RTF), or hyper-VLP (HVLP) copper foils with sub-2 micron surface profile cut this loss substantially.

Via Stubs

Every via that goes deeper than necessary creates a stub that resonates at a frequency dependent on stub length. A 3 mm stub resonates at approximately 25 GHz. The resonance creates a sharp notch in the channel frequency response that can cost 10 dB or more locally. Back-drilling removes stubs; un-back-drilled boards lose signal at via resonances regardless of laminate material. For high-speed work, back-drilling is generally as important as material selection.

Fibre Weave Skew

Differential pairs running parallel to the glass weave of an FR4 laminate can encounter different effective Dk on each leg of the pair — one trace sitting mostly over glass, the other mostly over resin. The result is propagation delay skew between the two legs of the pair, typically a few picoseconds per inch. At 25 Gbps, each picosecond is 2.5% of a unit interval. Mitigations include spread-glass laminate (1078, 1080 styles with mechanical glass spreading), routing at 10–20 degrees relative to the weave, or jittered routing. For 25G and above, address this in the stackup.

Connectors and Package Routing

Channel loss includes everything between transmitter die and receiver die, not just the PCB traces. Connectors typically eat 1–3 dB at the Nyquist frequency depending on grade. Package routing inside the IC adds another 2–4 dB at high speed. The PCB's share of the loss budget is typically 60–75%.

Mitigations: What Actually Works

Lower-Df Laminate

The most direct and effective mitigation. Stepping from FR4 (Df 0.020) to mid-loss (Df 0.010) cuts dielectric loss in half at every frequency. Stepping to low-loss (Df 0.004) cuts it by another factor of 2.5. The cost premium is real, but for designs above 10 GHz the alternative is non-function.

Smoother Copper Foil

For boards already on a low-loss laminate, the next biggest lever is copper foil. VLP foil cuts conductor loss by 30–50% compared to standard ED foil. HVLP cuts it further. For 56G PAM-4 and above, HVLP or RTF is essentially mandatory because dielectric loss has already been minimised and copper roughness becomes the dominant contributor.

Shorter Traces

Loss is linear in length. A 12 inch channel can be cut to 6 inches by routing strategy or by relocating the IC, and the loss is halved. For very critical channels in tight-loss-budget designs, trace length is a parameter to optimise, not just a side effect of layout.

Back-Drilling

Removes the stub resonance contribution. For boards above 16 Gbps, back-drilling on the longer vias is essential regardless of material choice. The cost is modest, the benefit is significant.

Hybrid Stackups

For designs where ultra-low-loss material is necessary on only a few signal layers, hybrid stackups combine the expensive material on signal layers with FR4 on power and ground. Total board cost drops substantially with no impact on critical-channel performance. Linked Electronics Co., Limited produces hybrid stackups routinely — Megtron 7 signal layers over an FR4 core is a typical pattern for cost-sensitive 56G PAM-4 designs.

Equalisation

The IC vendor's CTLE/DFE/FFE capabilities recover several dB of channel loss but are not infinite. Plan to consume roughly half of available equalisation budget at the laminate-selection stage so production variation does not push the channel into the inelastic region.

Frequency Conversion: When 10 GHz Becomes 28 GHz or 77 GHz

The 10 GHz threshold discussed throughout this article refers to high-speed digital signalling. For RF and microwave applications — mmWave 5G at 28 GHz or 39 GHz, automotive radar at 77 GHz, satellite communications above 60 GHz — the same physics applies but the operating frequencies are higher. The loss equation does not change. A material with Df 0.004 that gives 0.25 dB/inch at 12.5 GHz gives roughly 0.55 dB/inch at 28 GHz and 1.5 dB/inch at 77 GHz.

For mmWave designs, the high-frequency dielectric loss combines with substantial conductor loss to produce channel attenuation that can exceed 3–5 dB per inch on standard laminates. This is why mmWave designs use specialty materials — Rogers RO4350B, RO3003, RT/duroid series, Taconic — that are engineered for low loss at the relevant frequencies. The cost premium is significant but the alternative is no signal arriving at the antenna.

How to Run Your Own Loss Budget

Before specifying material, run a first-cut channel loss budget:

1. Identify the Nyquist frequency for your highest-speed channel — data rate divided by two for NRZ, baud rate divided by two for PAM-4.
2. Estimate dielectric loss using 2.3 × f(GHz) × sqrt(Dk) × Df × trace length (inches). Use 50% margin on the laminate's published Df to account for moisture, temperature, and lot variation.
3. Add conductor loss — roughly 0.3–0.6 dB/inch at 10 GHz on standard ED copper, 0.2–0.4 dB/inch on VLP, 0.15–0.3 dB/inch on HVLP.
4. Add via loss — 0.5–1 dB per via if back-drilled, 2–5 dB if not.
5. Add connector and package loss from vendor data — typically 3–6 dB combined.
6. Compare total to the IC vendor's specified maximum. If your estimate exceeds the spec, the channel will not work reliably. If it is within 3 dB of the spec, production variation will likely cause yield issues. Aim for at least 5 dB margin against the spec.

For projects where the first-cut budget is tight, Linked Electronics Co., Limited can review the proposed stackup, trace lengths, and material choice at quotation stage and provide a more detailed channel loss assessment using our materials data and historical measurements.

Frequently Asked Questions

Is 10 GHz a hard threshold above which FR4 stops working?

No, it is a practical inflection point. The reality is gradual — FR4 channels become progressively worse as frequency climbs, and the design margin gets thinner. By 10 GHz the margin is typically gone for any non-trivial trace length. Short FR4 channels can function above 10 GHz if length is well below 6 inches and equalisation is aggressive. The threshold is not a wall, but it is where most production designs migrate to better material.

Does Df really increase with moisture?

Yes, measurably. A laminate at equilibrium with 50% relative humidity at 25°C may have Df 10–30% higher than the dry datasheet value. The effect is more pronounced on hygroscopic resin systems and less on PTFE-based or ceramic-filled materials. For high-speed designs operating in humid environments (industrial, outdoor, automotive), the moisture-affected Df is the relevant number. Reputable vendors publish "after moisture exposure" Df values.

Can equalisation completely fix a high-loss channel?

No. CTLE and DFE boost specific high-frequency content but each has a finite boost limit beyond which boosting the signal also boosts noise to the point where the receiver cannot decide reliably. As a rule of thumb, modern SerDes receivers can recover perhaps 15–25 dB of channel loss with full equalisation engaged. Beyond that, the noise penalty exceeds the signal recovery. For PCIe Gen5 channels specified at 36 dB total insertion loss, the receiver's CTLE/DFE budget is mostly consumed.

If I have to ship now and cannot change material, what can I do?

Several options exist that do not require material change: shorten trace lengths by relocating components or rerouting, add or upgrade back-drilling on long vias, switch to smoother copper foil if possible, reduce data rate temporarily until next board revision, enable maximum receiver equalisation, and add stronger transmit pre-emphasis. None of these recover the channel as completely as a material upgrade but together they can buy several dB of margin.

Does Linked Electronics Co., Limited measure actual channel performance?

For customers requiring measured signal integrity verification, Linked Electronics Co., Limited supports test coupon fabrication with embedded loss measurement structures (typically TDR/VNA coupon designs). The coupon results are reported alongside the board shipment. For full S-parameter characterisation of customer-specified channels, we coordinate with third-party SI laboratories on request.

Are Chinese low-loss laminates as good as Megtron 6?

The major Chinese low-loss laminates (Shengyi S7439 in particular) have measured Df values close to imported equivalents at substantially lower cost. For most commercial high-speed work, they are credible alternatives. For mission-critical hyperscale or military programmes where lot-to-lot consistency must be statistically proven, imported materials are often still preferred. Linked Electronics Co., Limited stocks both and presents both options at quotation so customers can compare specifications and prices for their specific design.

How does this interact with PCB Class 2 vs Class 3?

IPC-6012 Class 2 vs Class 3 governs fabrication tolerances and inspection rigour, not material choice. A 25 Gbps channel on FR4 will fail signal integrity regardless of whether the board is Class 2 or Class 3 quality. Material selection addresses the electrical problem; Class selection addresses the reliability problem. Both must be specified for high-speed work.

What is the simplest way to know if I need to worry about Df?

If your fastest channel runs at 8 Gbps or below, you probably do not need to worry — FR4 will work. If your fastest channel runs at 16 Gbps or above, you almost certainly need low-loss or better material. The 8–16 Gbps range is where it depends on trace length and total loss budget; run a first-cut loss calculation, or send the project to Linked Electronics Co., Limited for review.

Why Choose Linked Electronics Co., Limited for High-Speed PCB Fabrication

Linked Electronics Co., Limited supports the full range of high-speed PCB laminates in our Suining facility — from standard FR4 through Megtron 6, Megtron 7, Tachyon 100G and 112G, Shengyi low-loss alternatives, Rogers RO4350B and RT/duroid, and various RF-specific materials. Our process engineers maintain qualified workflows for each material family, including the specialised lamination cycles, copper foil pairings, and impedance modelling that high-speed work demands.

For high-speed projects, Linked Electronics Co., Limited reviews the stackup, trace topology, via design, and intended data rate at the engineering quotation phase. Where channel loss budgets look tight, we propose material upgrades, copper foil alternatives, or hybrid stackup constructions and quantify the cost impact. Where the customer-specified material is over-engineered for the design, we suggest a lower-tier alternative with cost savings. The goal is a board that works on the first build and that is not over-spent on material.

If you have a 10 Gbps to 112 Gbps SerDes design, a high-frequency RF board, or any project where Df matters — send your stackup, trace lengths, and target data rate to [email protected]. Linked Electronics Co., Limited will return a material recommendation, channel loss assessment, and manufacturable quote within one to two business days.

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