Some PCB design rules are loud and visible. Trace width and clearance get checked by the DRC. Annular ring shows up in fabrication reports. Solder mask expansion is visible the moment you open the Gerber preview. Component courtyard clearance is none of these things. It is a dotted-line outline around each footprint that does nothing in simulation, nothing in DRC by default, and nothing for the board's electrical behaviour. So designers ignore it.
Then the boards arrive at SMT assembly. Two 0402 capacitors are sitting 0.15 mm apart, side by side. Pick-and-place places them. Reflow happens. Solder paste from one component bridges to the next during melting. AOI catches the defect. Rework starts. A second BGA reflow risks the first one. Yield drops. Customer asks why.
This article explains what the courtyard actually is, why it matters more than its quiet appearance suggests, and how Linked Electronics Co., Limited reviews courtyard violations during DFM at quotation stage to prevent them reaching the assembly line.
What the Courtyard Is
In IPC-7351 footprint terminology, every component has three concentric outlines:
- Body outline — the physical perimeter of the component package itself.
- Pad layout — the copper pads where the component solders to the board.
- Courtyard — a larger outline encompassing the body, the pads, and a clearance margin around them. The space inside the courtyard is reserved for that component; nothing else should enter it.
The courtyard is the keep-out region. Adjacent components, vias, traces on the same layer at the surface, silkscreen text, fiducials, mounting holes — none of these should encroach on another component's courtyard. The space between courtyards of adjacent components is what the assembly process actually needs to function reliably.
The key word is reliably. A board can usually be assembled with courtyards touching or even overlapping. But the process margin disappears, defect rates climb, and rework becomes physically difficult. The courtyard is not a hard physical constraint — it is the boundary where the assembly process stops being robust.
Why Courtyard Violations Cause Real Problems
Solder Bridging
Solder paste deposits are not perfectly bounded by stencil apertures — paste slumps slightly during reflow as flux activates and metal melts. When two pads on adjacent components sit within 0.15–0.20 mm of each other, the molten solder from one can flow into the other, creating a bridge that AOI catches but takes manual rework to fix.
Pick-and-Place Nozzle Clearance
The nozzle that picks and places a component has a physical diameter. For a 0402 or 0201 component, the nozzle tip is 1–2 mm wide. If the next component is already placed and sits within nozzle reach, the nozzle physically collides with it during placement — either knocking it out of position or refusing to descend, depending on the machine's safety logic. Linked Electronics Co., Limited's pick-and-place lines need at least 0.5 mm clear of any adjacent placed component for the nozzle to descend safely on 0402 placements, and more for larger nozzles.
Rework Tool Access
When a component fails inspection, rework requires a hot-air nozzle or solder iron to access it from above and the sides. If neighbouring components are tight against the courtyard, the rework hot air bleeds onto them, reflowing solder on parts that should not be disturbed. A BGA rework with components packed inside its courtyard is a yield-loss event waiting to happen — the BGA may be repaired but three adjacent capacitors lift, tombstone, or skew during the rework.
Optical Inspection Blocking
AOI cameras need clear lines of sight to component leads and solder joints. Tall components inside a low component's courtyard cast shadows or block the camera angle entirely, causing AOI to flag false defects or miss real ones. For X-ray inspection, dense neighbouring metal can scatter and obscure BGA joint imaging on the part being inspected.
Solder Paste Stencil Aperture Limits
Stencil apertures for fine-pitch components require minimum spacing between adjacent apertures, typically 0.1–0.15 mm of stencil material between adjacent openings. Two fine-pitch components inside each other's courtyards may require apertures so close that the stencil structurally cannot survive the squeegee stroke — paste deposits get inconsistent and the stencil wears prematurely.
The IPC-7351 Density Levels Explained
IPC-7351 (the standard governing surface mount footprints) defines three density levels — Level A, Level B, and Level C — corresponding to the assembly environment the board is designed for. The differences are real and affect the courtyard size for every footprint.
| Level | Name | Typical Courtyard Excess | Application |
|---|---|---|---|
| Level A | Most (Maximum land protrusion) | 0.5 mm or more around the pad envelope | Low-density boards; harsh environments; high-reliability work where rework margin is critical |
| Level B | Nominal (default) | 0.25 mm around the pad envelope | Standard commercial electronics; the IPC-7351 default and Linked Electronics Co., Limited recommendation for general work |
| Level C | Least (Minimum land protrusion) | 0.10 mm around the pad envelope | High-density consumer electronics; smartphones, wearables; controlled assembly process required |
The numbers in the table are typical values — IPC-7351 defines the courtyard excess separately for each component family (chip resistor, SOIC, QFP, BGA, etc.), and a modern CAD library will generate the correct courtyard automatically based on the chosen density level.
The choice between levels is not free. Level A gives generous assembly margin but uses board area inefficiently — useful for industrial control and harsh-environment work where rework is expected. Level C packs components tightly but requires SMT process control to match, AOI optimisation, and an assembly partner with relevant experience. Level B is the middle ground and the right default for most projects.
Specific Clearance Guidelines by Component Type
Beyond the IPC-7351 courtyard, certain situations need additional consideration. The values below are the practical minimums Linked Electronics Co., Limited applies during DFM review:
Chip Components (0201, 0402, 0603, 0805)
Adjacent passive components should have at least 0.3 mm of clear board between courtyards for Level B placement, or 0.2 mm for Level C. 0201 placement at sub-0.2 mm spacing requires high-end pick-and-place equipment and an experienced assembly process.
SOIC, QFP, and SOT Components
Allow at least 1.0 mm between the courtyard of a leaded package and any other component for routine work, or 0.5 mm in dense designs. The clearance is needed for the leaded body and for rework tool access.
BGAs and QFNs
Allow at least 2.0 mm clear of any component on all four sides of a BGA. This is non-negotiable for any BGA larger than approximately 10 mm square — the rework hot-air nozzle for BGA replacement is typically 30 mm in diameter, and surrounding components within 2 mm of the BGA are at high risk during any rework operation. For very fine-pitch BGAs (0.4 mm and finer), 3 mm or more is recommended.
Connectors and Through-Hole Parts
Connectors require clearance beyond their courtyard for the connecting cable, plug, or mating connector. The IPC courtyard does not capture this — it captures only the SMT process needs. For board-edge connectors, leave 3–5 mm clear of the connector body extending outward for cable routing. For through-hole connectors, allow 1.0 mm minimum between the connector courtyard and any adjacent SMT component, both for wave soldering selective process clearance and to prevent damage during connector insertion.
Tall Components
Electrolytic capacitors, large inductors, and shielding cans cast significant shadows for AOI and may interfere with X-ray angles. Keep at least 1.5 mm between tall components (over 3 mm height) and any fine-pitch component nearby.
Edge of Board
Components within 5 mm of the board edge are at risk during depanelisation, conveyor handling, and board flexing. Keep all components — particularly BGAs and fine-pitch parts — at least 5 mm from the board edge. The courtyard rule does not technically require this, but Linked Electronics Co., Limited treats it as a separate DFM requirement on every quotation.
The Courtyard Overlap Problem
The single most common courtyard violation is two adjacent footprints whose courtyards overlap. CAD tools typically warn about this with a DRC check, but the check is often disabled by default or set to warning-only. Designers see the warnings, decide they look fine in 3D preview, and ignore them.
The fix is straightforward: when DRC flags a courtyard overlap, treat it as a real warning. Either move one of the components, accept the violation knowingly and confirm with the assembly house that the process can tolerate it, or reduce density level locally (use Level C footprints) with full understanding of the assembly requirements.
What designers should never do is ignore the warning because the components fit physically. The courtyard captures the process margin, not the geometric fit. Linked Electronics Co., Limited routinely sees boards arrive where the components were physically placeable but the assembly line could not maintain yield because of courtyard violations.
When You Can Knowingly Violate Courtyard
There are legitimate reasons to compress courtyards beyond the IPC default. The key is that the violation should be knowing and discussed with the assembly partner in advance.
- Smartphone-class density. Modern phones routinely place 0402 and 0201 passives at courtyard-touching density. This works because the assembly process is dedicated, tightly controlled, and the boards never see rework — they are scrapped if they fail. For consumer electronics in tens of millions of units, this is the economic right answer.
- RF circuits. Decoupling capacitors next to an IC power pin sometimes need to be physically as close as possible for inductance reasons. Tight courtyard placement is justified by the electrical requirement, and the local SMT process can usually be tuned for it.
- Differential pair termination. Series resistors and termination components on high-speed differential pairs may need to be paired tightly. Same rationale — electrical need outweighs assembly margin, and the local layout is carefully controlled.
- Mechanical fit constraints. Sometimes the housing or connector mechanics dictate component placement that the IPC courtyard does not love. The right response is to discuss with the assembly partner and confirm what the process can tolerate, rather than guessing.
What turns courtyard violation from a known risk into a yield disaster is doing it accidentally or invisibly. The board arrives, assembly tries, defects appear, nobody knows why. The fix in that situation is much harder than catching it at DFM review.
How Linked Electronics Co., Limited Reviews Courtyard at DFM
During PCBA quotation, the Linked Electronics Co., Limited engineering team runs a DFM check that includes courtyard analysis. Specific items reviewed:
- Component-to-component courtyard overlaps, flagged by severity
- BGA periphery clearance — at least 2 mm clear of adjacent components
- Fine-pitch components (0201, 0.4 mm BGAs) — courtyard checked against our pick-and-place nozzle capability
- Tall component shadowing of fine-pitch parts
- Connector clearance for cable, mating connector, or operator access
- Edge-of-board clearance for depanelisation safety
- Mixed through-hole and SMT regions, where wave soldering selective access matters
Any violations are listed in the DFM feedback returned with the quotation, with severity (must-fix versus advisory), suggested corrections, and impact on yield or unit cost if uncorrected. Customers can choose to accept and proceed with knowledge of the risk, or revise the layout.
Frequently Asked Questions
If the components fit physically, why does courtyard matter?
Because the courtyard captures what the assembly process needs, not what the layout viewer shows. Pick-and-place nozzle clearance, paste reflow margin, rework tool access, AOI camera line of sight — none of these are visible in a 3D PCB preview. The courtyard is the IPC standard's way of expressing all of them in a single dotted-line outline.
Does my DRC catch courtyard violations automatically?
Most modern CAD tools (Altium Designer, KiCad, Allegro, Eagle, Mentor Xpedition) can check courtyard-to-courtyard overlap, but the check is often not enabled in default rule sets. Confirm in your DRC configuration that "Courtyard overlap" or equivalent is enabled as an error, not just a warning. Set the courtyard layer separately from silkscreen so it does not get cluttered by other annotations.
What density level should I design for if I am not sure?
Use Level B (nominal) for all general work. It is the IPC default, suits standard commercial assembly processes, and gives reasonable area efficiency without compromising process margin. Move to Level C only when board area is critical and you can confirm the assembly partner can handle it. Move to Level A only for harsh-environment or high-rework applications. Linked Electronics Co., Limited's default DFM target is Level B unless otherwise specified.
Does courtyard apply to through-hole components?
Yes. IPC-7351 covers surface mount, but a parallel concept applies to through-hole parts — pin-to-pin clearance, body-to-body clearance, and wave-solder selective access clearance. The principle is the same: leave room for the process, not just for the components.
What happens at assembly if I send a board with courtyard violations?
It depends on severity. Minor violations (a few hundred microns of overlap on passive components) may be accepted with a note about process risk; the board assembles but yield is somewhat below normal. Major violations (a 0.4 mm BGA with passives inside its keep-out region) typically result in DFM feedback requiring layout revision before fabrication. Linked Electronics Co., Limited flags the difference clearly and does not silently proceed with a high-risk layout.
Are courtyard rules different for prototype versus production?
The rules are the same; the tolerance for risk differs. A prototype is usually small quantity, often hand-reworked, and process margin matters less. A production build at 10,000 units cannot afford even a 1% yield loss from courtyard violations. Linked Electronics Co., Limited reviews accordingly — a violation that is acceptable on a 10-board prototype is a quote-stopping issue on a 50,000-board production order.
How do mounting holes interact with courtyard?
Mounting holes are typically defined with their own keep-out zones (for screw head clearance, washer area, or mechanical interference). These zones should be treated like courtyards — no components inside them. The mounting hardware also creates physical clearance requirements during board mounting that exceed the typical PCB courtyard, so allow generous margins around mounting holes regardless of the IPC density level chosen elsewhere.
Does Linked Electronics Co., Limited provide a sample DFM checklist?
Yes. We provide a DFM feedback report with every PCBA quotation that includes courtyard analysis, fiducial completeness, panelisation feasibility, fine-pitch placement review, and edge-clearance verification. For customers preparing their first board for SMT, we can share a pre-submission DFM checklist on request — contact [email protected].
Why Choose Linked Electronics Co., Limited for DFM-Reviewed PCBA
Linked Electronics Co., Limited treats DFM review as a standard part of quotation, not an optional service. Every Gerber and BOM submitted is reviewed by our engineering team for courtyard compliance, fiducial completeness, fine-pitch feasibility, and panelisation suitability. We return findings with the quote, before fabrication or assembly begins, so layout revisions cost layout time rather than rebuilt boards.
Our SMT lines operate IPC-7351 Level B as the default process target, with Level C high-density capability on selected production lines after engineering review. We support BGAs from 1.0 mm pitch down to 0.35 mm pitch, 0201 passive placement, fine-pitch QFN, and mixed surface-mount / through-hole assembly with selective wave soldering. Standard inspection includes AOI on every board, X-ray on every BGA-bearing board, and ICT or functional test on customer-specified builds.
If you are preparing a board for assembly — whether prototype or production — send your Gerber files, BOM, and pick-and-place files to [email protected]. Linked Electronics Co., Limited will return a DFM-reviewed quote within one to two business days, with any courtyard or assembly concerns flagged before the project starts.
Need a DFM-reviewed PCB and PCBA quote?
Linked Electronics Co., Limited provides courtyard, fiducial, fine-pitch, and panelisation review with every PCBA quotation — before fabrication begins.
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