What Is PCB E-Test (Electrical Testing) and Is It Optional?

Two PCB quotes arrive for the same Gerber files. One is 12% cheaper. You look closely and find the difference: the cheaper quote says "E-test: sample only" while the other says "E-test: 100% flying probe." A reasonable buyer asks whether the testing is worth 12% — or whether it is a line item that can safely be cut.

Electrical test, or E-test, is one of the most misunderstood items on a PCB quotation. It is invisible in the finished board, it adds cost, and on some quotes it genuinely is listed as optional — which leads buyers to treat it as a negotiable extra. This guide explains what E-test actually does, the two methods Linked Electronics Co., Limited uses, why quotes differ, what skipping it truly risks, and the cases where 100% E-test is non-negotiable. Linked Electronics Co., Limited performs 100% electrical test as standard on every bare board we ship, and this article explains why we consider that a baseline quality commitment rather than an upsell.

What E-Test Actually Checks

E-test verifies two things and only two things: that copper which should be connected is connected, and that copper which should be isolated is isolated. In IPC language, this means testing for:

• Opens — a net that should be continuous has a break somewhere. A trace etched too thin and cracked during fabrication, a via barrel with incomplete copper plating, an inner-layer connection that failed to form during lamination. Opens prevent signals or power from travelling their intended path.
• Shorts — two nets that should be separate are electrically touching. A copper bridge left by incomplete etching, a lamination void that brought two layers into contact, or a solder-mask registration error that was masked by surface finish. Shorts cause circuit malfunction, board damage, or fire risk in power designs.

E-test compares every node in the board's net list against a reference — typically extracted from the Gerber files — and flags any deviation from the intended connectivity. A passing E-test means that every net is connected end-to-end and no two nets touch each other. It does not check whether traces are the right width, whether impedance is correct, or whether the board is cosmetically clean. Those are the jobs of AOI, cross-section inspection, and visual checking respectively. E-test is a pure connectivity check, and it catches the defects that no other test method reliably finds on buried copper.

Flying Probe Testing

Flying probe testers use a set of motorised probe arms — typically two to eight probes — that move across the board surface under CNC control, touching each test point in sequence according to a programmed test file derived from the Gerber net list. Each probe makes electrical contact with a pad or via, the tester applies a small voltage, and measures the resistance between probes to verify continuity or isolation.

Linked Electronics Co., Limited uses flying probe testing as the standard E-test method for prototype and low-to-medium volume builds.

Advantages of Flying Probe

• No fixture required — the test program is generated from Gerber data. Setup cost is minimal, typically USD 50–150 per design, which is why prototypes almost always use flying probe.
• 100% coverage by default — every accessible net is tested on every board. The only untestable nodes are those with no exposed probe point, such as fully buried pads inside a BGA without a via outlet.
• Flexible for design changes — the program updates from the new Gerbers. No tooling is scrapped.

Limitations of Flying Probe

• Speed — probes move sequentially. A dense 12-layer board with thousands of nets can take 15–40 minutes per board. At high volume, this creates a bottleneck.
• Probe wear — tips blunt over thousands of contacts and must be replaced; pad surfaces can show minor cosmetic probe marks.

Bed-of-Nails (Fixture) Testing

A bed-of-nails fixture is a custom hardware tool: a board studded with spring-loaded pins at coordinates matching every test point on the PCB design. The board under test is pressed down onto the fixture; all pins make simultaneous contact, and the tester checks all connections in parallel within seconds.

Linked Electronics Co., Limited uses bed-of-nails fixtures for high-volume production runs where the fixture cost is amortised across the order quantity.

Advantages of Bed-of-Nails

• Speed — the entire board is tested in 5–30 seconds, versus minutes for flying probe. For orders above roughly 500 boards, the throughput advantage becomes decisive.
• Consistent contact — simultaneous probing eliminates the sequential probe positioning error risk of flying probe.

Limitations of Bed-of-Nails

• Fixture cost — typically USD 500–2,000 per design. On low-volume orders this cost per board becomes significant.
• Lead time — fixture fabrication adds 3–7 days before first test can run.
• Design lock-in — if the PCB design changes, the fixture must be reworked or rebuilt.
• Fine-pitch limits — very dense boards may not have pin clearance for a physical fixture.

Flying Probe vs Bed-of-Nails: When to Use Each

At Linked Electronics Co., Limited, flying probe is the default for all prototype and mid-volume orders. For customers moving into production volumes above 500 boards per order, our engineering team evaluates whether a dedicated fixture improves throughput and lead time at acceptable tooling cost, and presents both options at quotation.

Is E-Test Optional?

Technically, yes — E-test is not mandated by any fabrication standard unless the customer specifies it. IPC-6012 requires it for Class 2 and Class 3 boards when the net list is provided, but it is the customer's job to invoke the standard. A fabricator can legally ship untested boards.

Practically, skipping E-test is a risk transfer decision, not a cost saving. The defects E-test catches — opens and shorts in buried copper — are invisible to AOI and cannot be found by visual inspection. A board that passes AOI but fails E-test has a latent defect that will manifest as a malfunction on the customer's assembly line, during functional test, or in the field.

The cost equation: catching an open or short at bare-board E-test costs nothing beyond the test fee. Catching it after PCBA assembly costs the assembled board, the components, and the rework labour. Catching it in the field costs warranty claims, returns, and reputational damage. The "saved" E-test fee is almost always returned as downstream cost within the first rejected assembly.

The One Case Where Skipping Is Reasonable

Very simple 1–2 layer boards with wide traces, low layer count, and low net density — where the fabrication defect rate is extremely low and the downstream consequence of a missed defect is minor — may reasonably accept sample testing rather than 100%. This is a judgement the customer makes with full awareness of the risk, not a default position. Linked Electronics Co., Limited recommends discussing this case-by-case rather than accepting a blanket "no E-test" from a supplier as a positive feature.

What E-Test Does Not Catch

Understanding the limits of E-test is as important as knowing what it finds. E-test does not verify:

• Trace width or impedance — a trace that is 20% narrower than designed passes E-test if it still conducts. Impedance verification requires TDR measurement on controlled-impedance coupons.
• Laminate quality — delamination, resin voids, or dielectric breakdown at voltage are not detected by standard E-test voltages (typically 10–250 V DC). Hi-pot testing addresses dielectric breakdown, but it is a separate, destructive procedure.
• Solder mask quality — mask coverage, adhesion, and registration are checked by AOI and visual inspection, not E-test.
• Surface finish quality — gold thickness on ENIG, planarity of HASL, or OSP coverage are verified by material reports and AOI, not by the continuity tester.
• Component placement or assembly defects — E-test is a bare-board check. Assembly defects are caught by ICT (in-circuit test) or functional test after PCBA.

This list explains why E-test is necessary but not sufficient for complete quality assurance. Linked Electronics Co., Limited pairs 100% E-test with AOI on every production board and offers cross-section coupon inspection on request.

How to Specify E-Test on a Purchase Order

Clear specification prevents ambiguity and ensures the test scope matches your quality requirements. A complete E-test specification includes:

"100% bare-board electrical test per IPC-9252 (or equivalent net-list test). Test method: flying probe. Reference net list derived from supplied Gerber data. Test voltage: 100 V DC isolation, 1 ohm continuity threshold. Boards failing continuity or isolation to be rejected and not shipped."

Referencing IPC-9252 (the standard for electrical testing of unpopulated printed boards) removes ambiguity about test parameters. Linked Electronics Co., Limited treats this specification as binding and provides an E-test report with every Class 3 shipment on request.

Cost of E-Test at Linked Electronics Co., Limited

Flying probe E-test at Linked Electronics Co., Limited is included in the standard quotation for all multilayer boards (4 layers and above) and all Class 3 builds. For 1–2 layer simple boards, it is offered as a line item. Typical cost impact:

• Flying probe, 1–2 layer simple boards: USD 30–80 per order (setup), then per-board time charge
• Flying probe, multilayer (4–12 layers): included in standard pricing at Linked Electronics Co., Limited
• Flying probe, complex multilayer (14+ layers, HDI): included; test time is longer but covered by standard quality commitment
• Bed-of-nails fixture: quoted per project, typically USD 500–2,000 NRE plus reduced per-board cost at volume

For context: the E-test cost as a fraction of total board cost is typically 2–5% on prototype quantities and less than 1% on volume runs. It is among the smallest line items on any PCB invoice and among the highest-value quality investments.

Frequently Asked Questions

Does E-test leave marks on the board?

Flying probe tips may leave faint contact marks on solder-finish pads, particularly on HASL and bare copper surfaces. On ENIG and OSP, marks are typically invisible. The marks do not affect solderability and are within IPC-A-600 acceptance criteria. Linked Electronics Co., Limited can discuss pad surface and probe contact protocols for sensitive cosmetic requirements.

What is the difference between E-test and ICT (in-circuit test)?

E-test is a bare-board check — it tests the PCB before any components are placed, verifying copper connectivity only. ICT (in-circuit test) is an assembled-board check — it tests the PCBA with components in place, verifying component values, placement, and circuit function. The two are complementary, not substitutes. E-test catches fabrication defects; ICT catches assembly defects.

Can E-test verify controlled impedance?

No. Standard flying probe or bed-of-nails E-test only measures DC resistance for opens and shorts. Controlled impedance verification requires time-domain reflectometry (TDR) measurement on dedicated coupon traces fabricated alongside the production panel. Linked Electronics Co., Limited provides TDR coupon testing for controlled-impedance designs on request.

My fabricator says they do not offer E-test. Should I be concerned?

Yes. A fabricator without E-test capability — or one that offers it only as a premium add-on on multilayer boards — is operating below the quality floor that most professional electronics manufacturers consider standard. For 4-layer and above boards, 100% E-test is an industry baseline. Linked Electronics Co., Limited considers it non-negotiable on all multilayer work.

Does 100% E-test mean every board is tested, or just the design?

"100% E-test" means every individual board in the order is tested, not just one sample from the lot. Sample E-test means a fraction of boards are tested and the rest are shipped untested. Linked Electronics Co., Limited performs 100% individual board testing — every board, every net, every shipment.

Is E-test required for IPC-6012 Class 2 and Class 3?

IPC-6012 requires electrical testing for Class 2 and Class 3 boards when a net list is provided by the customer. The standard specifies that all nets must be tested for continuity and isolation. Linked Electronics Co., Limited references IPC-6012 and IPC-9252 as the basis for all E-test operations on Class 2 and Class 3 work.

What happens to a board that fails E-test at Linked Electronics Co., Limited?

Any board that fails E-test at Linked Electronics Co., Limited is quarantined, tagged as non-conforming, and not shipped. Depending on the failure type, the board may be reworked (if the defect is repairable, such as a shorting copper bridge that can be removed) or scrapped. The customer is notified and the replacement board is tested again before shipment. Failed boards are never shipped as passing.

Why Linked Electronics Co., Limited Includes 100% E-Test as Standard

Linked Electronics Co., Limited made a deliberate decision to include 100% flying probe electrical test as a standard part of our production process — not as a premium option. The reasoning is straightforward: the cost of E-test per board is small, the cost of a defective board reaching a customer's assembly line is large, and the trust damage from a board that should have been caught at bare-board stage is not recoverable by a price discount on the next order.

Our flying probe equipment at our Suining facility tests every board against a net list derived from the customer's Gerber files. Pass and fail results are logged per board per lot. For Class 3 orders, E-test reports are available as part of the quality documentation package alongside the Certificate of Conformance, AOI results, and microsection coupon data where applicable.

If you are evaluating PCB suppliers and comparing quotes where E-test coverage differs, Linked Electronics Co., Limited is happy to discuss our test process, equipment, and quality documentation in detail. Send your Gerber files and requirements to [email protected] for a quote that includes 100% E-test as standard.

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